Modular Veriication of Multipliers

We present a new method for the eecient veriication of multipliers and other arithmetic circuits. It is based on modular arithmetic like Kimura's approach, and on composition, like Hamaguchi's approach. It diiers from both in several important respects, which make it more robust. The technique builds the residue Algebraic Decision Diagram (ADD) of as many variables as the number of outputs in the multiplier and composes the implementation circuit from the outputs to the inputs into the residue. Finally, the residue ADD is checked against the speciication.